UL3524 Design Support¶
Overview¶
This repository provides AMD Alveo UL3524 card support including Vivado based reference designs targeting features of the card.
Reference Designs¶
Available reference designs are summarized in the following table. Each reference design includes:
High-level design overview including attributes, performance, limitations and usage
Simulation waveform files with waveform descriptions to better understand the design
Hardware design files along with ILA / VIO configuration files allowing greater control and visibility into the design
Each reference design is located in their respective sub-directory.
Reference Design |
Summary |
---|---|
Benchmark design used to measure and report GTF in MAC and RAW 10G latency. |
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Demonstrates how to setup the QSFP-DD Renesas device and route the GTF recovered clock through Bank 65. |
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DDR I2C and MIG bring-up and validation through PCIe. |
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Interface with the QDRII+ memory montroller through AXI. |
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Enable QSFP module power planes and side-band signals via I2C interface. |
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Program the Renesas devices via I2C using a state machine. Includes script to convert Renesas programming script file to |
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Example design which shows how to use a FINN-generated MLP IP block on the ULL |
Supported Cards¶
The following card is supported by the reference designs in this repository:
UL3524
Vivado Design Support¶
The reference designs require the following Vivado release:
Vivado ©️ 2023.1 or greater
The following links provide support on the Vivado flow:
The UL3524 Master Answer Record provides support resources such as known issues and release notes. For additional assistance, post your question on the AMD Community Forums - Alveo Accelerator Card.
Hardware Requirements¶
To program the device from the Vivado HW Manager, you need either of the following:
Micro-B USB cable
Alveo Debug Kit (ADK). See Alveo Accessories to purchase.
Support¶
For additional documentation, please refer to the UL3524 product page and the UL3524 Lounge.
For support, contact your FAE or refer to support resources at support.xilinx.com.