UL3524 Ultra Low Latency Trading

GTF Recovery Clock Routing Operation in Hardware¶

This section provides steps to run the GTF Recovery Clock Routing design on the UL3524 via the Vivado HW Manager.

The key steps to run the design are:

Program the device

Program the UL3524 with the bitstream (.bit) and ILA (.ltx).
(Optional) Enable ILA to capture and view waveforms

Load the Tcl helper functions
Initialize the GTF’s, configure the Jitter Cleaner, and enable and transfer a data stream
Check data integrity status

These steps are described in detail below.

Programming the Device¶

It is necessary to program the device with the reference design prior to running the design. Generate the design and create the bit file prior to following these steps.

Connect to the card via the HW Manager and program the FPGA with the following files:
- ./RECOV_CLK/Vivado_Project/<project_name>/<project_name>.runs/impl_1/clk_recov.bit
- ./RECOV_CLK/Vivado_Project/<project_name>/<project_name>.runs/impl_1/clk_recov.ltx
In the Vivado Tcl console, change the working directory to the following:
- cd ./RECOV_CLK/scripts/HwMgr
Use the following command to load the helper functions to control the board.
- source ./runme.tcl

Tcl Files¶

Once the project has been loaded, the design can be exercised using Tcl scripts found here. The scripts include setup, loading Renesas settings and measuring clock frequencies.

Support¶

For additional documentation, please refer to the UL3524 product page and the UL3524 Lounge.

For support, contact your FAE or refer to support resources at: https://support.xilinx.com

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