MLIR-AIE 1.4.5.dev
Class Hierarchy

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This inheritance list is sorted roughly, but not completely, alphabetically:
[detail level 1234]
 CAccessesLocalLocks
 CAcquireReleaseOneStateInDMABlock
 Cxilinx::AIE::Placer::Adjacency
 Cxilinx::AIE::StreamWaitGraph::AgentA core, a DMA channel, or a tile's controller
 CAIE2PElementwiseOps< OpTys >
 Cxilinx::aievec::AIE2PShufflePlanner
 Caie_libxaie_ctx_t
 Cxilinx::AIE::impl::AIEAssignBufferDescriptorIDsBase
 Cxilinx::AIE::impl::AIEAssignCoreLinkFilesBase
 Cxilinx::AIE::impl::AIEAssignLockIDsBase
 Cxilinx::AIE::impl::AIEAssignTileCtrlIDsBase
 Cxilinx::AIEX::impl::AIEBroadcastPacketBase
 Cxilinx::AIE::impl::AIECanonicalizeDeviceBase
 Cxilinx::AIEX::impl::AIECreateCoresBase
 Cxilinx::AIEX::impl::AIECreateLocksBase
 Cxilinx::AIEX::impl::AIECtrlPacketInferTilesBase
 Cxilinx::AIEX::impl::AIECtrlPacketToDmaBase
 Cxilinx::AIEX::impl::AIEDMATasksToNPUBase
 Cxilinx::AIE::impl::AIEFindFlowsBase
 Cxilinx::AIE::impl::AIEGenerateColumnControlOverlayBase
 Cxilinx::AIE::impl::AIELocalizeLocksBase
 Cxilinx::AIE::impl::AIELowerCascadeFlowsBase
 Cxilinx::AIEX::impl::AIELowerCoreResetBase
 Cxilinx::AIEX::impl::AIELowerDmaChannelResetBase
 Cxilinx::AIEX::impl::AIELowerMemcpyBase
 Cxilinx::AIEX::impl::AIELowerSetLockBase
 Cxilinx::AIEX::impl::AIEMaterializeBDChainsBase
 Cxilinx::AIEX::impl::AIEMaterializeRuntimeSequencesBase
 Cxilinx::AIEX::impl::AIEMulticastBase
 Cxilinx::AIE::impl::AIENormalizeAddressSpacesBase
 Cxilinx::AIE::impl::AIENormalizeDmaBdDimsBase
 Cxilinx::AIE::AIERTControl
 CAieRtControl
 Cxilinx::AIE::AIERTControl::AIERtImpl
 Cxilinx::AIE::AIETargetModel
 Cxilinx::AIEX::impl::AIETransformBfpTypesBase
 Cxilinx::aievec::impl::AIEVecConvAnalysisBase
 Cxilinx::AIEX::impl::AIEXToStandardBase
 Cargs
 CBankAwareContext
 CBdIdGenerator
 Caie_runtime::BdPool
 Cxilinx::AIEX::BdTemplateFields
 Cxilinx::AIE::BitFieldInfoBit field information for a register
 Cxilinx::AIEX::BlockwriteData
 Chrx_test::Buffer
 Cxilinx::AIE::BufferAllocation
 Cxilinx::aievec::BufferParams
 Cxilinx::AIE::SwitchboxConnect::Cell
 Chrx_test::ChainRun
 Cxilinx::AIEX::DmaQueueModel::ChannelStateOne channel's queue: its pushes not yet known to have completed, oldest first, each true when it issues a completion token
 CCircuitFanoutSeed
 Cxilinx::AIE::Placer::CollectedOps
 Cxilinx::AIE::NpuConfigCache::Config
 CConnectivityAnalysis
 Cxilinx::AIEX::ConstStridePolicy
 Chrx_test::Context
 CContractionTile
 CConversionPattern
 Cxilinx::impl::ConvertAIEVecToLLVMBase
 Cmlir::ConvertOpToLLVMPattern
 CLongestConvMACChainAnalysis::ConvMac
 CLongestConvMACChainAnalysis::ConvMacChainGroup
 Cxilinx::AIE::CoreTurnsThe order one core moves objects through several pools, read off its program, so that one DMA channel can serve those pools in turn
 Cd_ary_heap_indirect< Value, Arity, IndexInHeapPropertyMap, DistanceMap, Compare, Container >
 Cxilinx::aievec::AddElemOpAIE2Conversion::DecodedAddElemOp
 Cxilinx::aievec::MulElemOpAIE2pConversion::DecodedMulElemOp
 Cxilinx::aievec::MulElemOpConversion::DecodedMulElemOp
 Cxilinx::aievec::SubElemOpAIE2Conversion::DecodedSubElemOp
 Cllvm::DenseMapInfo< xilinx::AIE::DMAChannel >
 Cllvm::DenseMapInfo< xilinx::AIE::ObjectFifoAcquireOp >
 Cllvm::DenseMapInfo< xilinx::AIE::ObjectFifoCreateOp >
 Cllvm::DenseMapInfo< xilinx::AIE::Port >
 Cllvm::DenseMapInfo< xilinx::AIE::TileID >
 Cxilinx::AIE::DmaBdFieldBits [shift, shift + width) of register word in a buffer descriptor's register block
 Cxilinx::AIE::DmaBdLayoutThe register layout of one tile type's DMA buffer descriptor
 Cxilinx::AIE::DMAChannelAnalysisWhich DMA channels of each tile are already spoken for, so that a channel is handed out at most once across everything that programs one
 Cxilinx::AIE::DmaChannelProgramThe BD chain a DMA channel runs, as one aie.dma_start, aie.dma or runtime task programs it
 Cxilinx::AIEX::DmaCompletionStateCompletion is distinct from queue occupancy: Task_Queue_Size excludes the running task
 Cxilinx::AIEX::DmaQueueModelTracks, per DMA channel, the pushes not yet known to have completed along one execution path
 Cxilinx::AIE::DynamicTileAnalysis
 Cxilinx::AIE::ShimTransferSpans::EndA shim end a runtime sequence transfers through
 Cllvm::ErrorInfo
 Cxilinx::AIE::EventInfoEvent information
 CEventMonitor
 Cext_mem_model_t
 Cxilinx::AIE::Flow
 Cllvm::GraphTraits< const WaitGraph * >
 Cstd::hash< xilinx::AIE::Port >
 Cstd::hash< xilinx::AIE::TileID >
 CHasSomeParent< ParentOpTypes >
 CHasSomeTerminator< TerminatorOpTypes >
 Cxilinx::AIE::HoldCycleA cycle of waits packet streams can deadlock in, given their routes
 Cxilinx::AIE::Pathfinder::RouteState::IdSplit
 CInBuf< T >
 Cstd::less< xilinx::AIE::Port >
 CLiftedOps
 Chrx_test::LoadedKernel
 CLongestConvMACChainAnalysisThis analysis builds the longest possible chain of MAC operations whose operands are a vector that may or may not be shifted, and a broadcast
 Cxilinx::aievec::MatMulRecipe
 Cxilinx::AIE::MemoryRun
 Cxilinx::AIE::NamedOpTable
 Cxilinx::AIE::NamedOpTableCollection
 CNarrowingResult
 Cxilinx::AIEX::NdDmaPatternInnermost-first ND access pattern (d0..d3 / repeat), matching the convention used by verifyStridesWraps and NpuDmaMemcpyNdOp verification
 Cxilinx::AIE::NetBoundingBox
 Cxilinx::AIE::NetInfo
 Cxilinx::aievec::ShufflePlan::Node
 Cxilinx::AIE::NpuConfigCache
 Cmlir::OffsetSizeAndStrideOpInterface
 Cmlir::detail::OffsetSizeAndStrideOpInterfaceTrait
 COpConversionPattern
 COpRewritePattern
 COutBuf< T >
 Cxilinx::AIE::PacketConstraints
 Cxilinx::AIE::PacketIdSpaceThe packet ids a device has already spoken for
 Cxilinx::AIE::PacketsApart
 Ctest_utils::ParameterScratchpad
 Cmlir::PassPipelineOptions
 CPassWrapper
 Cxilinx::AIE::PathEndPoint
 Cxilinx::AIE::Pathfinder
 CPinnedOverlayWhat the prioritized flows take routed alone (see has_ctrl_pkt_overlay)
 Cxilinx::AIE::Placer
 Cxilinx::AIEX::DmaCompletionState::Push
 CPyAieTargetModel
 Cxilinx::AIEX::QueueEffectWhat one op in a loop body does to a channel queue
 Cxilinx::AIE::RegisterDatabaseRegister and event database for a specific architecture
 Cxilinx::AIE::RegisterInfoRegister information
 Cxilinx::AIE::ResetConfig
 Cxilinx::aievec::ResolvedMatMulOperand
 CRewritePattern
 Cxilinx::AIE::RoutedStreamOne stream from a source tile port to a destination tile port, recovered from the physical switchbox and shim-mux configuration
 Cxilinx::AIE::Pathfinder::RouteState
 Cxilinx::AIE::Routing
 Cxilinx::AIE::RoutingFaults
 CRuntimeCallGraphCyclicityAnalysis
 Cxilinx::AIE::SAConfig
 Cxilinx::AIE::SASchedule
 Cxilinx::AIE::ShimTransferSpansWhen the runtime sequences have each shim end's transfers in flight, so that ends never in flight together can take turns on one shim channel
 Cxilinx::aievec::ShuffleGather
 Cxilinx::aievec::ShuffleModeShape
 Cxilinx::aievec::ShufflePlan
 Cxilinx::aievec::ShuffleRequest
 Cxilinx::AIEX::SsaStridePolicy
 Cxilinx::AIE::HoldCycle::Step
 Cxilinx::AIE::StreamConflictsThe streams a device asks for or already routes, and which pairs of them must not share an arbiter or a link
 Cxilinx::AIE::StreamDeadlockAnalysisWhich streams can deadlock against each other if they share an arbiter or a link
 Cxilinx::AIE::StreamDemand
 Cxilinx::AIE::StreamEndpointA tile port at the edge of the stream fabric
 Cxilinx::AIE::StreamHopA switchbox a stream passes: the port it enters by and, where it is packet switched there, the arbiter it takes
 Cxilinx::AIE::StreamVolumeAnalysisHow much data a stream carries over a run and how much a receiver takes in before it has to wait on another agent, read off BD lengths, repeat counts, lock initial values and runtime transfers
 Cxilinx::AIE::StreamWaitGraphWhich agent waits on which
 Cxilinx::AIE::StreamWindow
 Cxilinx::AIE::StreamWindowStep
 Cxilinx::AIE::StructuralGraphOps and the labelled links between them, for ranking them by structure where a pass would otherwise fall back on op order
 Cxilinx::AIEX::SubviewTraceResult
 Cxilinx::AIE::SwitchboxConnect
 Cxilinx::AIE::SwitchSetting
 Cxilinx::AIEX::TaskBdDecompositionHow aie-decompose-large-dma-bd splits a runtime task's descriptor
 Cxilinx::AIE::TileAvailability
 Cxilinx::AIE::TileDMAChannelOne DMA channel of one tile
 Cxilinx::AIE::TileMemoryLimitsA memtile is reached by DMA rather than by core vector load and store, so its bus width also covers the vector-alignment requirement
 Cxilinx::AIEX::TokenAnalysis
 Cllvm::GraphTraits< const WaitGraph * >::ToNode
 Cmlir::OpTrait::TraitBase
 Cxilinx::AIE::Pathfinder::TreeBuilder
 Cxilinx::AIE::TreeHop
 Cxilinx::AIE::TreeSplit
 Caie_runtime::TxnDeviceInfo
 Cxilinx::AIE::TxnLocBracket
 Cxilinx::AIE::TxnLocEntry
 Cmlir::Type
 Cmlir::TypeConverter
 CUsesOneLockInDMABlock
 CVia